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1 high performance 1a ldo isl78310 the isl78310 is a low dropout voltage, high-current, single output ldo specified for 1a output current. this part operates from input voltages down to 2.2v and up to 6v. the part offers fixed and external resistor adjust able output voltages from 0.8v to 5v. custom voltage option s are available upon request. for applications that desire to se t the in-rush current to less than the current limit of the part, or for applications that require turn-on time control, an external capacitor can be placed on the soft-start pin for maximum control. a supply-independent enable signal allows the part to be placed into a low quiescent current shutdown mode. sub-micr on cmos process is used for this product family to deliver best-in-class analog performance and overall value. this cmos ldo consumes significant lower quiescent (ground pin) current as a function of load over bipolar ldos, which translates into higher efficien cy and packages with smaller footprints. quiescent current is optimized to achieve a very fast load transient response. the isl78310 is both aec-q100 rated and fully ts16949 compliant. the isl78310 is rated for the automotive temperature range (-40c to +125c). applications ?core & i/o power ? camera modules ? post regulation of switched supplies ? radio systems ? infotainment systems features ? 2.2v to 6v input supply ? 130mv dropout voltage typical (at 1a) ? fast load transient response ? 0.2% initial v out accuracy ? adjustable in-rush current limiting ? 58db typical psrr ? 63v rms output noise at v out = 1.8v ? power-good feature ? 500mv feedback voltage ? supply-independent 1v enable input threshold ? short-circuit current protection ? 1a peak reverse current ?over-temperature shutdown ? any cap stable with minimum 10f ceramic ? 1.8% guaranteed v out accuracy for junction temperature range from -40c to +125c ? available in a 10 lead dfn package ? pb-free (rohs compliant) ? aec-q100 tested ? ts16949 compliant pin configuration isl78310 (10 ld 3x3 dfn) top view 2 3 4 1 5 9 8 7 10 6 vout vout sense/adj pg gnd vin vin nc enable ss pad caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. february 17, 2011 fn7810.0
isl78310 2 fn7810.0 february 17, 2011 pin descriptions pin number pin name description 1, 2 vout regulated output voltage. a minimum 10f x5r/x7r output capacitor is required for stability. see ?external capacitor requirements? on page 9 for more details. 3 sense/adj for internally fixed v out option, this pin provides output voltage feedback . by connecting this pin to the output rail at the load, small voltage drops caused by pcb trace resistance can be eliminated. for the adjustable output voltage optio n, this pin is connected to the feedback resistor divider and provides voltage feedback signals for the ldo to set the outpt voltage. 4 pg this is an open drain logic output used to indicate the status of the output voltage. logic low indicates v out is not in regulation. must be grounded if not used. 5gndground. 6 ss external capacitor on this pin adjusts startup ramp and controls in-rush current. 7enable v in independent chip enable. ttl and cmos compatible. 8 nc do not connect this pin to ground or supply. leave floating. 9, 10 vin input supply pin. a minimum 10f x5r/x7r input capacitor is required for stability. see ?external capacitor requirements? on page 9 for more details. epad epad at ground potential. soldering it directly to gnd plane is required for thermal considerations. see ?heatsinking the dfn package? on page 11 for more details. ordering information part number (notes 1, 3, 4) part marking v out voltage (note 2) temp range (c) package (pb-free) pkg dwg. # isl78310arajz dzae adj -40 to +125 10 ld 3x3 dfn l10.3x3 ISL78310ARAJZ-TR5303 dzae adj -40 to +125 10 ld 3x3 dfn l10.3x3 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. for other output voltages, contact intersil marketing. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 4. for moisture sensitivity level (msl), please see device information page for isl78310 . for more information on msl please see techbrief tb363 .
isl78310 3 fn7810.0 february 17, 2011 typical application diagrams figure 1. fixed typical application diagram figure 2. adjustable typical application diagram note: 5. used when large bulk capacitance required on v out for application. v in pg enable ss gnd sense/adj v in v out 1 2 3 5 4 7 9 10 6 10k 100k 10f 2.5v 10% 1.8v 1.8% v out isl78310 (note 5) 10f v in pg enable ss gnd v in v out 1 2 5 4 7 9 10 6 10k 100k 10f 10f 2.5v 10% 1.8v 1.8% sense/adj 2.6k 1k v out isl78310 (note 5)
isl78310 4 fn7810.0 february 17, 2011 isl78310 schematic block diagram ? vin vout
isl78310 5 fn7810.0 february 17, 2011 absolute maximum rating s thermal information vin relative to gnd (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v vout relative to gnd (note 6). . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v pg, enable, sense/adj, ss relative to gnd (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v recommended operating conditions (notes 9, 10) junction temperature range (t j ) (note 9) . . . . . . . . . . . .-40c to +125c vin relative to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2v to 6v vout range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mv to 5v pg, enable, sense/adj, ss relative to gnd . . . . . . . . . . . . . . . 0v to +6v pg sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10ma thermal resistance . . . . . . . . . . . . . . . . . . . . ja (c/w) jc (c/w) 10 ld dfn package (notes 7, 8) . . . . . . . . 48 7 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2500v machine model (tested per jesd-a115-a) . . . . . . . . . . . . . . . . . . . . . 250v charge device model (tested per jesd22-c101c). . . . . . . . . . . . . . 1000v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6v of 1%. 7. ja is measured in free air with the componen t mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 . 8. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 9. extended operation at these conditions may compromise reliabi lity. exceeding these limits will result in damage. recommended operating conditions define limits where specifications are guaranteed. 10. electromigration specification defined as lifetime average junc tion temperature of +110c where max rated dc current = lifet ime average current. electrical specifications unless otherwise noted, v in = v out + 0.4v, v out = 1.8v, c in = c out = 10 f, t j = +25 c, i load = 0a. applications must follow thermal guidelines of the package to determine worst case ju nction temperature. please refer to ?isl78 310 schematic block diagram? on page 4 and tech brief tb379 . boldface limits apply over the op erating temperature range, -40c to +125c. parameter symbol test conditions min (note 11) typ max (note 11) units dc characteristics dc output voltage accuracy v out v out options: 0.8v, 1.2v, 1.5v and 1.8v 2.2v v in < 3.6v; 0a < i load 1a -1.8 0.2 1.8 % v out options: 2.5v, 3.3v and 5.0v v out + 0.4v v in 6v; 0a < i load < 1a -1.8 0.2 1.8 % feedback pin (adj option only) v adj 2.2v v in 6v, 0a < i load < 1a 491 500 509 mv dc input line regulation v out / v in v out + 0.5v < v in < 5v 1 % dc output load regulation v out / i out 0a < i load < 1a, all voltage options -1 % feedback input current v adj = 0.5v 0.01 1 a ground pin current i q i load = 0a, 2.2v < v in < 6v 3 5 ma i load = 1a, 2.2v < v in < 6v 5 7 ma ground pin current in shutdown i shdn enable pin = 0v, v in = 6v 0.2 12 a dropout voltage (note 12) v do i load = 1a, v out = 2.5v 130 212 mv output short circuit current ocp v out = 0v, 2.2v < v in < 6v 1.75 a thermal shutdown temperature tsd 2.2v < v in < 6v 160 c thermal shutdown hysteresis (rising threshold) tsdn 2.2v < v in < 6v 30 c ac characteristics input supply ripple rejection psrr f = 1khz, i load = 1a; v in = 2.2v 58 db f = 120hz, i load = 1a; v in = 2.2v 72 db output noise voltage i load = 1a, bw = 10hz < f < 100khz 63 v rms
isl78310 6 fn7810.0 february 17, 2011 enable pin characteristics turn-on threshold 2.2v < v in < 6v 0.3 0.8 1 v hysteresis (rising threshold) 2.2v < v out + 0.4v < 6v 10 80 200 mv enable pin turn-on delay c out = 10f, i load = 1a 100 s enable pin leakage current v in = 6v, en = 3v 1 a adjustable inrush current limit characteristics current limit adjust i pd v in = 3.5v, en = 0v, ss = 1v 0.5 1 1.3 ma i chg -3.3 -2 -0.8 a pg pin characteristics v out pg flag threshold 75 85 92 %v out v out pg flag hysteresis 4% pg flag low voltage v in = 2.5v, i sink = 500a 100 mv pg flag leakage current v in = 6v, pg = 6v 1 a notes: 11. compliance to datasheet limits is assured by one or more methods: production test, ch aracterization and/or design. 12. dropout is defined by the difference in supply v in and v out when the supply produces a 2% drop in v out from its nominal value. electrical specifications unless otherwise noted, v in = v out + 0.4v, v out = 1.8v, c in = c out = 10 f, t j = +25 c, i load = 0a. applications must follow thermal guidelines of the package to determine worst case ju nction temperature. please refer to ?isl78 310 schematic block diagram? on page 4 and tech brief tb379 . boldface limits apply over the op erating temperature range, -40c to +125c. (continued) parameter symbol test conditions min (note 11) typ max (note 11) units
isl78310 7 fn7810.0 february 17, 2011 typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. figure 3. v out vs temperature figure 4. v out vs supply voltage figure 5. v out vs load current figure 6. ground current vs supply voltage figure 7. ground current vs load current figure 8. dropout voltage vs temperature -1.8 -1.2 -0.6 0 0.6 1.2 1.8 -50-25 0 255075100125150 junction temperature (c) v out (%) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0246 supply voltage (v) v out (v) 135 +125c +25c -40c -1.8 -1.2 -0.6 0 0.6 1.2 1.8 0 0.25 0.50 0.75 1.00 load current (a) v out (%) +125c +25c -40c 0 1 2 3 4 5 24 input voltage (v) ground current (ma) 356 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 0 0.25 0.50 0.75 1.00 load current (a) ground current (ma) -40c +125c +25c 0 20 40 60 80 100 120 140 160 180 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) dropout voltage (mv) v out = 2.5v i load = 1a i load = 500ma i load = 100ma
isl78310 8 fn7810.0 february 17, 2011 figure 9. load transient response figure 10. enable start-up figure 11. psrr vs frequency figure 12. spectral noise density vs frequency typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. (continued) 20s/div 1a 1ma di/dt = 4a/s voltage rails at 50mv/div v in = 3.7v, v out = 3.3v, c out = 10f, c pb = 100pf v in = 2.9v, v out = 2.5v, c out = 10f, c pb = 82pf v in = 2.5v, v out = 1.8v, c out = 10f, c pb = 82pf v in = 2.5v, v out = 1.5v, c out = 22f, c pb = 150pf v in = 2.5v, v out = 1.2v, c out = 47f, c pb = 270pf v in = 2.5v, v out = 1.0v, c out = 47f, c pb = 220pf ? enable v out (1v/div) ss (1v/div) pg (1v/div) (2v/div) (500s/div) 0ma 100ma 500ma 1a 0 10 20 30 40 50 60 70 80 90 100 1k 10k 100k 1m frequency (hz) psrr (db) v in = 2.5v, v out = 1.8v, c out = 10f, c pb =82pf 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1m 10m frequency (hz) i load = 1a spectral noise density (v/ hz)
isl78310 9 fn7810.0 february 17, 2011 applications information input voltage requirements isl78310 is capable of delivering output voltages from 0.8v to 5.0v. due to the nature of an ldo, v in must be some margin higher than the output voltage plus dropout at the maximum rated current of the application if active filtering (psrr) is expected from v in to v out . the generous dropout specification of this family of ldos allows applications to design for a level of efficiency that can accommodate profiles smaller than the to220/263. external capacitor requirements general guideline external capacitors are required for proper operation. careful attention must be paid to layo ut guidelines and selection of capacitor type and value to ensure optimal performance. output capacitor the isl78310 applies state-of-the -art internal compensation to keep the selection of the output capacitor simple for the customer. stable operation over full temperation, v in range, v out range and load extremes are guar anteed for all capacitor types and values assuming a minimum of 10f x5r/x7r is used for local bypass on v out . this output capacitor must be connected to the v out and gnd pins of the ldo with pcb traces no longer than 0.5cm. additional capacitors of any value in ceramic, poscap, alum/tantalum electrolytic types may be placed in parallel to improve psrr at higher frequenc ies and/or load transient ac output voltage tolerances. input capacitor for proper operation, a minimu m capacitance of 10f x5r/x7r is required at the input. this ceramic input capacitor must be connected to v in and gnd pins of the ldo with pcb traces no longer than 0.5cm. phase boost capacitor (c pb ) a small phase boost capacitor, cpb, can be placed across the top resistor in the feedback resistor divider network (figure 13 below) in order to place a zero at: this zero increases the crossover frequency of the ldo and provides additional phase result ing in faster load transient response. it is also important to note that the ldo stability and load transient are affected by the type of output capacitor used. for optimal result, empirical tuning of c pb is suggested for each specific application. it is recommended to not use c pb when high esr capacitors such as aluminum elec trolytic or tantalum are used. table 1 shows the recommended c pb, r top , r bottom and c pb values for different output voltage rails. thermal fault protection in the event the die temperature exceeds typically +160c, then the output of the ldo shuts down until the die temperature cools down to typically +130c. the level of power, combined with the thermal resistance of the package (+48c/w for dfn), determines whether the junction temperature exceeds the thermal shutdown temperature specified in the ?electrical specifications? table on page 5 (see thermal packaging guidelines). (eq. 1) f z 12pir top c pb ? ? ? () ? = table 1. v out (v) r top (k ? ) r bottom ( ? ) c pb (pf) c out (f) 5.0 2.61 287 100 10 3.3 2.61 464 100 10 2.5 2.61 649 82 10 1.8 2.61 1.0k 82 10 1.5* 2.61 1.3k 68 10 1.5 2.61 1.3k 150 22 1.2* 2.61 1.87k 120 22 1.2* 2.61 1.87k 270 47 1.0 2.61 2.61k 220 47 0.8 2.61 4.32k 220 47 *either option could be used, depending on cost/performance requirements. isl78310 c in r top r bottom c pb v in v out en ss pg c out adj figure 13.
isl78310 10 fn7810.0 february 17, 2011 current limit protection the isl78310 ldo incorporates protection against overcurrent due to any short or overload condition applied to the output pin. the current limit circuit performs as a constant current source when the output current exceeds the current limit threshold noted in the ?electrical specific ations? table on page 5. if the short or overload condition is removed from v out , then the output returns to normal voltage mode regulation. in the event of an overload condition on the df n package, the ldo will begin to cycle on and off due to the die temperature exceeding thermal fault condition. functional description enable operation the enable turn-on threshold is typically 0.8v with a hysteresis of 80mv. the enable pin does not have an internal pull-up or pull-down resistor. as a result, this pin must not be left floating. this pin must be tied to v in if it is not used. a pull-up resistor (typically 1k to 10k ) will be required for applications that use open collector or open drain outp uts to control the enable pin. the enable pin may be connected directly to v in for applications that are always on. soft-start operation the soft-start circuit controls the rate at which the output voltage rises up to regulation at power-up or ldo enable. this start-up ramp time can be set by adding an external capacitor from the ss pin to gnd. an internal 2 a current source charges up this c ss and the feedback reference voltage is clamped to the voltage across it. the startup time of the regulator output voltage for a given c ss value can be calculated using equation 2. the soft-start function also effe ctively limits the amount of in- rush current to less than the programmed current limit during start-up or an enable sequence, to avoid an over current fault condition. this can be an issue for applications that require large, external bulk capacitances on v out where high levels of charging current can be seen for a significant period of time. high in-rush currents can cause v in to drop below minimum, which could cause v out to shutdown. t ramp c ss x0.5v 2 a ------------------------- = (eq. 2) figure 14. in-rush current with no c ss , c out = 1000f, in-rush current = 1.8a figure 15. in-rush current with c ss = 15nf, c out = 1000f, in-rush current = 0.5a figure 16. in-rush current with c ss = 33nf, c out = 1000f, in-rush current = 0.2a
isl78310 11 fn7810.0 february 17, 2011 equation 3 can be used to calculate c ss for a desired in-rush current, where v out is the output voltage, c out is the total capacitance on the output, and i inrush is the desired in-rush current. the scopes in figure 14 to 33 capture the response for the soft- start function. the output voltage is set to 1.8v. the external capacitor is always discharged to ground at the beginning of start-up or enabling. power-good operation the pgood is a logic output that indicates the status of v out . the pgood flag is an open-drain nmos that can sink 10ma during a fault conditio n. the pgood pin requir es an external pull- up resistor, which is typically connected to the vout pin. the pgood pin should not be pulled up to a voltage source greater than v in . pgood goes low when the output voltage drops below 84% of the nominal output voltage or if the part is disabled. the pgood comparator fuctions duri ng current limit and thermal shutdown. for applications not using this feature, connect this pin to ground. output voltage selection an external resistor divider is used to scale the output voltage relative to the internal reference voltage. this voltage is then fed back to the error amplifier. the output voltage can be programmed to any level between 0.8v and 5v. an external resistor divider, r 1 and r 2 , is used to set the output voltage as shown in equation 4. the recommended value for r 2 is 500 to 1k . r 1 is then chosen according to equation 5. power dissipation the junction temperature must not exceed the range specified in the ?recommended operating cond itions? on page 5. the power dissipation can be calculated by using equation 6: the maximum allowed junction temperature, t j(max), and the maximum expected ambient temperature, t a(max), will determine the maximum allowable power dissipation, as shown in equation 7: ja is the junction-to-ambient thermal resistance. for safe operation, ensure that the power disspiation p d , calculated from equation 6, is less than the maximum allowable power dissipation p d(max) . heatsinking the dfn package the dfn package uses the copper ar ea on the pcb as a heat-sink. the epad of this package must be soldered to the copper plane (gnd plane) for heat sinking. figure 17 shows a curve for the ja of the dfn package for different copper area sizes. general powerpad design considerations figure 18 shows the recommended use of vias on the thermal pad to remove heat from the ic. this typical array populates the thermal pad footprint with vias spaced three times the radius distance from the center of each via. small via size is advisable, but not to the extent that so lder reflow becomes difficult. all vias should be connected to the pad potential, with low thermal resistance for efficient heat transfer. complete connection of the plated-through ho le to each plane is important. it is not recommended to use ?thermal relief? patterns to connect the vias. c ss v out xc out x2 a () i inrush x0.5v ------------------------------------------------- - = (eq. 3) v out 0.5v r 1 r 2 ------ - 1 + ?? ?? ?? = (eq. 4) r 1 r 2 v out 0.5v ------------ - 1 ? ?? ?? = (eq. 5) p d v in v out ? () i out v in i gnd + = (eq. 6) p dmax () t jmax () t a ? () ja ? = (eq. 7) figure 17. 3mmx3mm 10 ld dfn on 4-layer pcb with thermal vias ja vs epad-mount copper land area on pcb 46 44 42 40 38 36 34 ? figure 18. pcb via pattern
isl78310 12 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7810.0 february 17, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl78310 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 2/17/11 fn7810.0 initial release.
isl78310 13 fn7810.0 february 17, 2011 package outline drawing l10.3x3 10 lead dual flat package (dfn) rev 6, 09/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip. lead width applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 5 6 6 a b 0.10 c 1 package 1.00 0.20 8x 0.50 2.00 3.00 (10x 0.23) (8x 0.50) 2.00 1.60 (10 x 0.55) 3.00 0.05 0.20 ref 10 x 0.23 10x 0.35 1.60 outline max (4x) 0.10 ab 4 c m 0.415 0.23 0.35 0.200 2 4

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